Semiconductor power devices typically include thousands of identical "active" cells, such as double-diffused metal-oxide-semiconductor (DMOS) transistors or insulated gate bipolar transistors (IGBT). These transistors are capable of controlling large voltages and currents at their cathode and anode terminals.
Shown in FIG. 1 is a single IGBT cell located near the die edge 48 of a known IGBT power device 10. The power device 10 includes a P+ substrate (collector) 12, an N+ epitaxial buffer layer 14, and an N- epitaxial layer (base) 16. For each cell (of which there are usually many), a P-well (emitter) 18 is formed in the N- epitaxial layer 16. An N+island forms an emitter diffusion 20 in the P-well 18, and both are contacted by emitter metal 22 that overlies the entire device 10. A P+ island 24 is formed through the P-well 18 and into the N- epitaxial layer 16 to provide good ohmic contact between the emitter metal 22 and the P-well 18 and enhance the ruggedness of the device. Gate polysilicon 26 overlies but is electrically insulated by a gate oxide 44 from a region of the P-well 18 between the N+ emitter diffusion 20 and the N- epitaxial 16. The collector (P+ substrate) 12 is positively biased via collector metal 46, and the emitter (P-well 18, P+ island 24 and N+ emitter diffusion 20) is grounded. The base (N- epitaxial 16) of the power device 10 is not charged by any external means.
The power device 10 is turned on by applying a positive voltage to the gate polysilicon 26 via a gate metal field plate 36, which causes the surface of the P-well 18 beneath the gate polysilicon 26 to invert and form an n-type channel through which electrons flow from the grounded N+ emitter diffusion 20 toward the positively-biased P+ substrate 12. At this stage, the device 10 behaves as a MOSFET, with the N+ island (emitter diffusion 20) serving as the source, and the N- epitaxial layer 16 serving as the drain for electrons. In this mode, the cells of the device 10 have a common source (emitter metal 22), drain (N- epitaxial layer 16) and gate (gate polysilicon 26). As electrons cross the diode formed by the P+ substrate 12, N+ buffer layer 14 and N- epitaxial layer 16, the diode becomes forward biased (i.e., the N- epitaxial layer (base) 16 becomes negatively charged) and starts to inject holes from the P+ substrate 12 into the N- epitaxial layer 16. The holes are then drawn to the grounded P-well 18 and P+ island 24, thereby effectively turning the device 10 "on."
The IGBT power device 10 depicted in FIG. 1 is generally a punch-through device--the voltage at breakdown (and below) will "deplete" or punch all the way through the epitaxial layer 16--to reduce the thickness of the N- epitaxial layer 16 required to meet the forward blocking voltage requirement for the device. The device 10 is shown as having an edge termination structure that includes a low-voltage ring 28 a continuous high-voltage N+ well 30. The low-voltage ring 28 has a continuous P+ well 34 that underlies but is electrically insulated from the gate polysilicon 26 by a field oxide layer 38, such that the gate polysilicon also forms a gate terminal of the P+ well 34. A continuous high-voltage metal ring 42 contacts the N+ well 30 through the field oxide layer 38 and a low temperature oxide (LTO) layer 40 for the purpose of terminating the device 10, providing a channel stop, improving breakdown voltage and reducing leakage, and, for clamped devices, making contact to the high-voltage epitaxial layer 16.
The P+ well 34 and N+ well 30 are located near the edge of the die and completely encircle the cells of the power device 10. The N+ well 30 is spaced up to 50 micrometers, typically 20 .mu.m, from the die edge 48, with the P+ well 34 being spaced about 200 .mu.m from the N+ well 30. Because they are continuous, the N+ well 30 and particularly the P+ well 34 serve to reduce the high electric fields that occur in the sharp corners of the die. As such, the presence of the continuous P+ well 34 and N+ well 30 enables the device 10 to sustain high voltages when in the "off" state.
As stated above, in the forward direction the diode between the P+ substrate 12 and the N- epitaxial layer 16 (referred to here as the "substrate diode") is forward biased. In the reverse direction, a typical device of the type shown in FIG. 1 will have a breakdown voltage (BV) of about 20 V to 50 V. This provides voltage blocking, but only up to the breakdown voltage of the substrate diode. The ruggedness of the Power device 10 is generally defined as the ability of the device to resist failure when its breakdown voltage is exceeded. The active area of the power device 10 is surrounded by the edge termination structure (ring 28 and well 30) in order to increase the breakdown voltage of the device 10. However, many IGBT applications, such as automotive ignition systems, have reverse power transients or pulses that exceed the reverse breakdown voltage for the device 10, and these transients often have sufficient energy to cause the device 10 to be destroyed. The typical location for breakdown of the substrate diode is at the edge of the die, indicated by the reference number 32 in FIG. 1. Once current flows at this location, it continues up to the N +well 30 and then over to the emitter metal 22 through the P+ well 34 of the low-voltage ring 28.
In view of the above, an IGBT semiconductor power device is required that exhibits improved resistance to reverse power pulses.